Electric timing circuits



Oct. 29, 1968 L ETAL 3,408,539 v ELECTRIC TIMING CIRCUITS 2 Sheets-Sheet 1 Filed April 22, 1966 HG INVENTORS MALcoLm Lesa Jun: BPm-mcnsou Leann-Aka M. WEDEPOHL.

ATTQRNEYS 0d. 29, 19 8 M. LEGG ETAL 3,408,539

ELECTRIC TIMING CIRCUITS Filed April 22, 1966 2 Sheets-Sheet 2 89 as 33 i 9741 93 72 94 27 3: 82 90 92 26 F F 23 R 36 81 l 24 85 99 22 34 .8 I P 1 80 g? 1 32- i 12\}: 'M

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'NVENTOQS MALcoLm LEGS JOHN B.- PATRICKSON Leann-mm: "LWEDEPOHL ATTDRNEYJ 1 United States Patent 3,408,539 ELECTRIC TIMING CIRCUITS Malcolm Legg and John Brian Patrickson, South Shields,

and Leonhard Martin Wedepohl, Disley, England, assignors to A. Reyrolle & Company Limited, Hebburn, England, a company of Great Britain Filed Apr. 22, 1966, Ser. No. 544,583 Claims priority, application Great Britain, Apr. 23, 1965, 17,292/65 3 Claims; (Cl. 317-36) ABSTRACT OF THE DISCLOSURE Timing circuits are provided for producing a delay in the generation of a control signal in response to an initiating signal by means of integrating circuits. An initiating circuit is included for providing a constant pre-charge to the integrating circuit and a discharging network is provided for discharging the integrating circuit to a voltage below that produced by the constant pre-charge to insure that the integrating circuit is always activated at a constant starting voltage. An input signal shaping circuit may be included for providing an initiating signal proportional to a selected function of the input current and to provide a time lag in the generation of the control signal that is inversely proportional to the selected function of the input current.

This invention relates to electric timing circuits including an integrating capacitor, means for charging it progressively, from what may be termed an initiating moment, and means responsive to the capacitor voltage reaching a predetermined value.

The invention is applicable to a wide variety of systems requiring a consistent and repeatable time interval under different conditions. In particular it is applicable to protective systems, control systems or signalling or telemetry systems, and can be adapted for time intervals of a very Wide range of durations from fractions of a millisecond or less, to hundreds of seconds or more.

One application of the invention is to protective systems in which the timing circuit forms part of a delayed time lag relay for introducing delay before the tripping of circuit breakers after an initiating signal has been supplied to the timing circuit from an initiating circuit. The initating circuit may of course respond to various different conditions or parameters.

According to the present invention the circuit is characterized by means for imparting to the capacitor an initial charge to a predetermined low voltage substantially instantaneously at the initiating moment. For example the timing charge may be obtained from a timing supply in which case the initial charge may be obtained from a comparatively low voltage supply through a diode. The low voltage supply may be afforded by a potential divider connected across the timing supply. In one arrangement the potential divider includes at least one diode.

Preferably the means responsive to the capacitor voltage comprises a trigger circuit controlling an output circuit.

Preferably the discharge of the capacitor is effected by the cessation of the input signal. In this case, if the input signal should cease before triggering occurs, the capacitor will be discharged to give a full delay period when the next input signal occurs. Preferably the discharge path is of sutiiciently low resistance to discharge the capacitor comparatively rapidly (in relation to the delay time) down to. a voltage less than that of the low voltage supply.

In one form of the invention the capacitor forms part of a resistor capacitor integrating network. In an alternalive form of the invention the capacitor forms the feedback capacitor of a Miller integrator.

The invention may be put into practice in various ways but certain specific embodiments will be described by Way of example with reference to the accompanying drawings, in which:

FIGURE 1 isa circuit diagram of a definite time lag relay, employing an RC integrator, for a protective system;

FIGURE 2 is a similar circuit employing at Miller integrator and capable of being used either for a definite time lag or for an inverse time lag relay; and

FIGURE 3 is a similar circuit of a further arrangement primarily intended for an inverse time lag relay.

In each case the arrangement includes an initiating circuit which forms no part of the present invention and will not be described in detail. The initiating circuit may be arranged to close contacts and keep them closed to connect a supply to the timing circuit from the initiating moment when the relevant condition subsists. Alternatively, in accordance with the present applicants patent specification No. 544,449, filed April 22, 1965, the initiating contacts may close only for part of each cycle or halfcycle of an alternating supply, from the time that the relevant condition subsists. 1

In the arrangement of FIGURE 1 the initiating circuit responds to over current and its output includes a reed type relay 10 which is energised when the initiating circuit responds to over current and then closes its contacts 11 and keeps them closed, in order to initiate a timed period.

The timing circuit is energised from a timing supply represented by a pair of Zener diodes 12 connected to.a D.C. supply 14 (for example of 50 volts) in series with a resistor 15 and with the initiating contacts 11 of the reed relay of the initiating circuit.

In this particular case the purpose of the Zener diodes is to provide a reduced voltage. In fact the value of the voltage is not critical to the operation, and if a lower voltage supply is employed the Zener diodes 12 may be omitted.

Connected across the timing supply represented by the Zener diodes is a resistor capacitor network comprising a resistor 19 in series with the timing capacitor 20. Accordingly when a signal is received from the initiating circuit, that is to say when the reed contacts 11 close, a timing supply is established and the timing capacitor 20 begins to charge up through the resistor 19.

Connected to the junction 21 of the resistor capacitor network is a trigger circuit comprising a pair of transistors 22 and 23, one NPN and the other PNP, each having its base connected to the collector of the companion transistor. The PNP transistor 22 has its emitter connected to the tapping of a potential divider 24, 25 connected across the supply, and its base (and the collector of the NPN transistor) connected to the junction 21 of the resistor capacitor network.

The emitter of the NPN transistor 23 is connected through a resistor 26 to the base of an output transistor 27 of N PN type having its emitter connected to the negative terminal of the timing supply and its collector connected through an output realy coil 30 to the positive terminal of the supply. The output relay coil 30 is shunted by a diode 31 and controls contacts 32 connected across a suitable supply 33 in series with a holding relay coil 34 and a tripping coil 36. The holding relay has contacts 37 in parallel with the output relay contacts 32.

The two trigger transistors operate with a snap action in known manner. Thus initially when the timing capacitor 20 is uncharged the base of the PNP transistor 22 is at substantially the same potential as the positive terminal of the supply whereas the emitter is more negative due to the drop in the resistor 25 of the potential divider 24, 25 connected across the supply.

As the junction 21 of the resistor capacitor network, and with it the base of this transistor, becomes more negative, 21 point is reached at which this transistor 22 begins to pass current. This current being injected into the base of the companion transistor 23 results in an amplified current being fed back to the base of the first transistor, so that both transistors rapidly become fully conducting. Thus current is injected into the base of the output transistor which conducts fully to energize the output relay. When the initiating contacts 11 open again, the timing capacitor will be discharged through the base emitter circuit of the PNP transistor 22 and the positive portion 25 of the potential divider connected to its emitter.

The arrangement so far described has the disadvantage that if there is any initial charge on the timing capacitor the delay period will be correspondingly reduced. This may occur in various ways. First of all, as pointed out above, the normal low-impedance path for the discharge of the timing capacitor is through the base emitter path of the transistor 22. This offers an easy path for current until the voltage falls to a certain low value, generally referred to as the toe value, after which the impedance greatly increases. Hence the capacitor voltage will fall rapidly to a low value, possibly of the order of half a volt, after which further discharge will occur much more slowly through a comparatively high impedance path including the resistance 19 of the resistor capacitor network and the whole of the potential divider 24, 25. Accordingly complete discharge of the capacitor will be delayed, and if a further initiating signal should be re ceived during this period the delay period will correspondingly be reduced. The capacitor may also acquire an initial charge due to the phenomenon known as dielectric absorption. With certain types of capacitor it is found that although the capacitor will naturally be discharged if a short circuit is placed across its terminals, none the less when the short circuit is removed a voltage difference can gradually re-appear between its terminals.

To overcome these difiiculties, in accordance with the present invention, means is provided for imparting to the capacitor an initial charge to a predetermined low voltage substantially instantaneously at the initiating moment. The term substantially instantaneously is used in this connection to mean in a period that is short in relation to the total time lag period. Thus a further potential divider is connected across the supply and its tapping is connected to the junction 21 of the resistor capacitor network through a precharging diode 41. In addition to two resistors 42 and 43 the potential divider may also include .a pair of diodes 44 and 45 at its positive end poled so as to permit flow of current through the potential divider from the supply.

The toe voltage of one of these diodes serves to compensate for that of the precharging diode 41, whilst that of the other compensates for that of the PNP trigger transistor 22. By including these diodes rather than relying solely on the resistors the compensation can be maintained under conditions of varying temperature.

Thus when the supply is switched on by the initiating circuit the capacitor is rapidly charged to a comparatively low voltage through the diode 41 and potential divider 42 to 45. The time taken for this to occur is negligible in comparison with the delay period imposed by the timing circuit. As soon as the capacitor has been charged to a voltage corresponding to that of the potential divider 42 to 45 the latter plays no further part in the operation of the circuit and any discharge through the potential divider is prevented by the precharging diode 41. The values of quantities involved may vary in accordance with requirements but by way of example if a charge of some 12 volts is required to actuate the .4 trigger circuit the initial charge might be of the order of a volt.

In the arrangement described above the timing capacitor forms part of a resistor capacitor integrating network. In a further embodiment shown in FIGURE 2 it forms the feedback capacitor of a Miller integrator. Brieflythis comprisesan amplifier, conveniently consisting of these transistors 50, 51 and 52 in cascade, of which the output transistor 52 is connected across the supply in series with an emitter resistor 53 and a pair of collector resistors 54 and 55. The base of the input transistor is connected to the positive supply terminal through one of a pair of timing resistors 56 and 57, selected by a switch 58, and through the timing capacitor 60 to the collector circuit of the output transistor 52.

When the supply is switched on, the circuit operates in the manner of a normal Miller integrator and the output voltage obtainable from the collector of the output transistor progressively rises. This is supplied to any suitable output trigger circuit so as to respond when the voltage reaches a predetermined value.

With the arrangement so far described the discharge of the capacitor when the power supply is switched ofi, would occur comparatively slowly through the output and input resistors 55 and 56 or 57 and the supply, or a path connected across the timing circuit. For reasons connected with other requirements it is inconvenient to make this complete path of low impedance and in particular it may be desirable to make the input impedance variable in order to provide a variety of different time delay periods.

To overcome this a pair of diodes 61 and 62 are included connecting the two terminals of the timing capacitor respectively to the terminals of the timing circuit. Thus one diode 62 is in parallel with the output resistor 55 and the other diode 61 is in parallel with the input resistor 56 or 57. When the supply is switched ofi these diodes provide rapid discharge of the capacitor down to a voltage of approximately half a volt for each diode (known as the toe voltage of the diode) at which their impedance rapidly rises. Thereafter the capacitor will discharge much more slowly through the input and output resistors. In order to prevent this from introducing variation in the delay period, in accordance with the present invention, the capacitor is connected to the junction between the two collector resistors 54 and 55 of the output transistor rather than directly to the collector of that transistor.

The operation of the integrator differs somewhat from that of the normal Miller integrator. In the latter, assuming for example that it comprises an output stage comprising a transistor with its emitter connected to an earthed negative supply terminal, then, provided the amplification is adequate, any flow of input current into the input of the amplifier will produce a change of output current suificient to ensure that a feedback current will flow back through the capacitor sufficient to nullify such input current. Thus in efiect the capacitor will accept substantially the whole of the input current and the input point of the amplifier will remain at constant potential, for example will be a virtual earth.

In practice various conditions must be met in order that the integration may be of a given degree of accuracy. It is not dilficult to provide sufiicient amplification to ensure that the input current flowing into the amplifier is only a very small proportion of the total input current and that the latter is only a very small proportion of the output current.

In a practical circuit such as that of FIGURE 2, even assuming that the emitter resistor 53 is omitted and the emitter of the output transistor is connected direct to the positive supply terminal, the potential difierence across the output transistor 52 can never quite start from zero. First there will always be a certain voltage difference between the base and emitter of each transistor known as the toe voltage and usually of the order of half a volt, so that there will always be a voltage of about 1 /2 volts between the base of the input transistor and the emitter of the output transistor. Secondly some feedback current flow through the capacitor is needed to keep the transistor fully conducting.

These difficutlies are met in accordance with the present invention by connecting the feedback capacitor, not directly to the collector of the output transistor 52, but to the tapping of the output transistor collector resistor Accordingly when the supply is switched on with the the initial feedback current will impotential and no further feedback current would flow and no further charging of the capacitor would take place to charge it even when the transistors are ing.

Accordingly the capacitor charges up comparatively rapidly to a voltage dependent on the value of the resistor 54 quite independently of any input current. This voltage is arranged to be in excess of the combined toe voltages of the three transistors.

The input current may be obtained in various ways depending on requirements. The circuit of FIGURE 2 is intended for a fixed time lag and accordingly the input current is obtained by applying a constant voltage to the input resistor 56 or 57. For this purpose instead of being connected directly to the positive supply terminal a potential divider connected across the supply.

This not only provides an input current but in addition it provides a path through which the capacitor can be immediately discharged through the diodes 61 and 62 when the supply is switched oil. In addition the base voltage of the input transistor 50 will be made up not only of the toe voltages of the three transistors but of those voltages plus the drop across the portion 53 of the potentiometer and hence will be less affected by variations of the toe voltages (due to temperature or changes of transistors).

The collector of the transistor 52 is connected through a potentiometer 64 to the positive supply terminal and the tapping is connected to the input of a combined amplifier and trigger circuit comprising four PNP transistors 65, 66, 67 and 68. The first three of these are connected in cascade, the emitter of each to the base of the next, the first two sharing a common collector resistor 69. The third and fourth transitsors 67 and 68 share a common emitter resistor 70 connecting their emitters to the positive supply terminal, and the collector of the third transistor 67 is connected through a resistor 71 and a Zener diode 72 to the base of the fourth transistor 68 so as to form a trigger circuit of the known Schmidt type.

The collector circuits of the third and fourth transistors 67 and 68 are interchangeable. One includes a resistor 73 while the other includes a resistor 74 in series with the coil of a relay 75, both being shunted by a diode 76.

Thus in operation the voltage across the potentiometer 64 gradually buids up until the transistors 65, 66 and 67 conduct and the transistor 68 cuts off. If delayed operation is required the relay will be placed in the collector circuit of the transistor 67, by suitable manipulation of links 77 or the like, whereas if delayed reset is required it will be placed in the collector circuit of the transistor 68 as shown.

The arrangement shown in FIGURE 2 is intended to give a constant delay time and accordingly the input resistor is connected direct to the positive supply terminal while the emitter of the output transistor 52 is connected to the tapping of the potentiometer 53, 63, so that a constant potential difference is applied to the input resistor. If it is required to give a time lag varying inversely as an input quantity, the base of the input transistor may be connected to the positive supply terminal through an input resistor in series with input terminals to which the said input signal is applied.

For such a requirement it is, however, preferred to employ the circuit shown in FIGURE 3, in which fuller use is made of the possibilities of employing NPN transistors as well as PNP transistors.

The circuit shown in FIGURE 3 is intended for an inverse definite minimum time lag relay, and while it employs a Miller integrator as in FIGURE 2 the trigger circuit is virtually the same as that of FIGURE 1 and corresponding parts bear the same reference numerals.

As in FIGURE 2 the circuit is energised from the initiating circuit but a shaping circuit generally indicated by the reference numeral 80 is connected to an input 81 from a current transformer, and through a resistor 82 to the negative supply terminal and through a diode 83 to the positive supply terminal, while its output is connected to the base of a transistor 85 of PNP type forming the input to the Miller integrator. By including suitable components in known manner, the shaping circuit 80 can provided suitable characteristic time delays of the form IT =K, I T=K of British Standard Specification No. 142.

The transistor 85 has its emitter connected to the positive supply terminal and its collector connected through a resistor 87 to the base of a second transistor 88, of NPN type, which in turn is connected through a capactior 89 to the negative supply terminal. The emitter of the transistor 88 is connected to the negative supply terminal while its collector is connected through a resistor 90 to the base of a third transistor 91 of PNP type. The emitter of the transistor 91 is connected to the positive supply terminal while its collector is connected through a pair of resistors 92 and 93 to the negative supply terminal. The junction point 94 between the two collector resistors 92 and 93 is connected to the positive supply terminal through a potentiometer 95 and is also connected through a feedback capacitor 96 to the base of the first transistor 85. The junction point 94 and hence one terminal of the capacitor is connected through a diode 97 to the negative terminal of the supply while the other terminal of the capacitor, and hence the base of the first transistor 85, is connected through a diode 98 to the positive supply terminal. The tapping of the potentiometer 95 is connected through a diode 99 t0 the input of a trigger circuit which is similar to that of FIGURE 1 and bears the same reference numerals.

As compared with the circuit of FIGURE 2 that of FIGURE 3 has the advantage that the emitter of the input transistor is connected to the positive supply terminal so that the voltage of its base differs from that of this terminal by only a single toe voltage of perhaps half a volt, which can be balanced by the use of a resistor and a diode, and the potentiometer 53, 63 of FIGURE 2 is not required. Similarly the emitter of the output transistor 91 is connected directly to the positive supply terminal. This means that a greater proportion of the supply voltage, determined by the Zener diodes 12, is available for timing since the available range is not reduced by dropping part of its across the portion 53 of the potential divider.

In each of the arrangements described above the circuit is energised by the input signal. In an alternative arrangement it may be continuously energised from a separate supply, the initiation of the time delay being etfected for example by a circuit including a switching device shunted across the capacitor.

It will be appreciated that the invention is not limited to the specific embodiments described by way of example. In particular where reed type relays have been described they may in general be replaced byother suitable typesof relay .or by statlc crrcults for example transistor circuits. Where a switching action is required it may be provided by employing a circuit of suflicient sensitivity or by employing a trigger or bistable circuit.

What we claim as our invention and desire to secure by Letters Patent is:

1. A timing circuit for providing a delayed control signal in response to an initiating signal comprising:

a source for providing power to the timing circuit, said source including first and second terminals,

a Miller integrator including a transitsor amplifier, in-

tegrating capacitor, an input terminal and first and second output terminals, said second output terminal being connected to said second terminal,

an input circuit for providing an initiating signal to the timing circuit, said input circuit being connected between said input terminal and said second terminal,

an output circuit connected across said source and to said output terminals, said output circuit including a pair of resistors connected in series between said first output terminal and said first terminal,

said integrator including a pair of diodes, said capacitor connected between said first and second terminals in series with and between said diodes, said diodes being poled to rapidly discharge said capacitor in response to the termination of the initiating signal, and

said output circuit further including means for interconnecting said input terminal with the junction of said pair of resistors to rapidly charge said capacitor to a pre-selected voltage prior to the application of the initiating signal. 3

2. A timing circuit as claimed in claim 1 further comprising current transformer means connected to the input circuit to provide an initiating signal proportional to a selected function of the current input to the input circuit and to provide a time lag in the generation of the control signal that is inversely proportional to the selected function of the current.

3. A timing circuit as claimed in claim 1 wherein said amplifier comprises first, second and third transistors connected in a cascade arrangement, .said first and third transistors including at least base and emitter electrodes, the emitter electrodes of said first and third transistors being connected to the same source termials so that the operating voltage difference between the base electrode of the first transistor and the emitter elecetrode of the third transistor is only a single toe voltage.

References Cited UNITED STATES PATENTS 3,127,542 3/1964 Riebs 317-22 3,262,017 7/1966 Ashenden et al. 317-36 X 3,317,791 5/1967 Price et al 317-36 3,346,797 10/1967 Baude 3201 JOHN F. COUCH, Primary Examiner. J. D. TRAMMELL, Assistant Examiner. 

